FIG. 1 shows a differential driver 1 that takes a differential input on conductors 2 and 3 and converts that input into a serial data stream on an output conductor 4.
It is known to use the differential driver 1 of FIG. 1 as an input stage to a digital system, but other circuits for that purpose are known. It is also known to generate a clock signal for the digital system from an input data stream (i.e. on the output 4 of the differential driver 1 in the case of FIG. 1). Such clock recovery is especially effective when the data changes frequently as this makes it easier to determine where the clock pulses should be positioned.
FIG. 2 shows a single data stream and an associated clock signal. The clock signal shown in FIG. 2 samples the data on both the rising and falling clock edges and the clock transitions are closely aligned with the mid-point between data transitions. Such alignment is preferable as the data is given the maximum time both before and after the clock transition in which to be stable. This gives the best chance of the set-up and hold times of subsequent circuits not being violated.
One method of achieving such clock alignment uses the circuit of FIG. 3. A phase locked loop (PLL) 5 is shown with an input 7 receiving a reference clock signal at the required frequency (or a sub-multiple of the required frequency). The PLL generates a number of clock outputs 8 (8 in the example of FIG. 3) each at a difference phase (spaced apart by 45 degrees in the example of FIG. 3). The clock signal can be placed close to the mid-point between the data transitions by selecting the most appropriate clock signal from the output 8 of the PLL 7.
Another method of determining the optimum clock signal is illustrated by FIGS. 4 and 5. FIG. 4 shows a phase wheel with 8 phase signals indicated, representing the eight phases of the PLL output 8. Those phase signals are plotted at 0, 45, 90, 135, 180, 225, 270 and 315 degrees respectively. The phase of data stream relative to a reference signal (for example, relative to a reference clock input) can be plotted on the phase wheel. Once the phase of data stream is “plotted” on the wheel, the outputs 8 of the PLL that are located either side of the data stream can be identified.
FIG. 5 is a block diagram of a circuit for generating the appropriate clock signal. The output of the differential driver 1 is passed to a phase detector 9 that determines the phase of the data (for example, with reference to the phase of the generated clock signal). Phase detector 9 stores the phase value and this is output to a phase interpolator 10 along with the eight clock signals from the PLL 7. A clock signal is generated by selecting the two phase signals from the PLL 7 between which the phase of the data stream falls and using the phase interpolator to generate a clock signal with a phase between those two clock signals. A typical phase interpolator may generate the most appropriate clock phase between those phase inputs from 16 possibilities. Thus the phase wheel can be divided into 16×8 (i.e. 128) clock phases.
The incoming data stream may be at a high frequency; in one optic fibre application the data rate is 3.2 Gb/s. A clock is recovered at 1.6 GHz and samples the data on both the rising and falling edges of the recovered clock signal (as shown in FIG. 2). It is preferable to have a clock signal that samples data on both the rising and falling edges only since a clock that sampled on the rising edge only would have to be at twice the frequency; this would double the power required by the circuit and double the noise present, which at those frequencies would be a practical limitation. Data sampled on the rising edge of the bit clock is termed “even” data and data sampled on the falling edge is termed “odd” data.